1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) technology, and more particularly, to a method for adjusting an oscillator in a PLL, and related frequency synthesizers.
2. Description of the Prior Art
For many kinds of communication devices (such as mobile phones), Multi-Mode/Multi-Band applications are increasingly utilized, and a mobile communication device often uses a frequency synthesizer with a wide frequency adjusting range for providing required clock signals in this type of application.
In general, the frequency synthesizer is realized by using a phase-locked loop (PLL) scheme. The gain value of an oscillator in the PLL of the frequency synthesizer should be maintained at a low level so as to meet a strict requirement for the phase noise in the mobile communication standard. In order to attain the above purpose, most oscillators of the frequency synthesizer are realized by using a switched capacitor voltage-controlled oscillator (switched capacitor VCO) so as to increase the frequency adjusting range of the frequency synthesizer.
It is known that the locking speed of the PLL has a large influence on the whole efficiency of the frequency synthesizer. Thus, how to improve the locking speed of the PLL that uses a switched capacitor oscillator scheme is a problem requiring a solution.